1 single port, plc differential line driver ISL15100 the ISL15100 is a single port differential line driver developed for power line communication (plc) applications. the device is designed to drive heavy line loads while maintaining the high level of linearity required in ofdm plc modem links. with 15.5dbm of total transmit signal power into 100 line load, the driver achieves -43db aver age mtpr distortion across the output spectrum up to 86mhz. the ISL15100 has two bias curre nt control pins (c0, c1) to allow for four power settings (disable, low, medium, high). in disable mode, the line driver outputs maintain a high impedance in the presence of high receive signal amplitude, so it doesn?t affect tdm receive signal integrity. the ISL15100 is available in the thermally-enhanced 16 ld qfn and is specified for operation over the full -40c to +85c ambient temperature range. features ? single differential driver ? 100mhz broadband plc g.hn, eoc, homeplug av2 ? control pins for enable/disable and supply current selection ? high output impedance when disabled for tdm operation ? -43dbc average mtpr distortion at full line power ? single +12v or bipolar 6v nominal supplies ? high surge current handling capability applications ? power line communication differential driver ? pin compatible upgrade to isl1571irz related literature ? an1325 ?choosing and using bypass capacitors? table 1. alternate solutions part # nominal v s (v) bandwidth (mhz) applications isl1571 6, +12 200 homeplug av1 figure 1. typical application circuit figure 2. 50mhz plc spectrum 3.9 1k +12v + - afe 1k + - 133 ? ISL15100 ? ISL15100 3.9 100 nominal line 1:2 typical differential i/o line driver 2.2n vcm 500 500 100n 100n supply decoupling not shown rf rf rg frequency (mhz) power (dbm ) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 2 7 12 17 22 27 32 37 42 47 september 19, 2013 fn8577.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL15100 2 fn8577.0 september 19, 2013 connection diagram ordering information part number (notes 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # ISL15100irz 151 00irz -40 to +85 16 ld qfn l16.4x4h ISL15100irz-t7 (note 1) 151 00irz -40 to +85 16 ld qfn l16.4x4h ISL15100irz-t13 (note 1) 151 00irz -40 to +85 16 ld qfn l16.4x4h ISL15100eval1z evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL15100 . for more information on msl please see tech brief tb363 . +12v + - + - 1:2 inb- ina- outa outb ina+ inb+ bias current control ? c0 c1 + ? ISL15100 ? +6v 133 500mvp 11.8vp into 100 + ? ISL15100 8.0vp 3.9 3.9 p line 1k 1k txmn cf = 15.4db p line = 16dbm av = 1 + 2 x 1000 133 = 16(v/v) 140 differential receiver path load at txmn input 500 500 figure 3. typical differential amplifier i/o
ISL15100 3 fn8577.0 september 19, 2013 pin configuration ISL15100 (16 ld qfn) top view 1 3 4 15 nc ina- ina+ gnd outa nc vs+ outb 16 14 13 2 12 10 9 11 6 578 nc inb- inb+ c1 nc nc vs- c0 ep* *exposed thermal pad connects to most negative supply pin descriptions pin number pin name function ep thermal pad connect to the most negative supply 1 nc no internal connection 2 ina- amplifier a inverting input 3 ina+ amplifier a non-inverting input 4gndground 5 nc no internal connection 6 nc no internal connection 7v s - negative supply voltage (-6v for split supplies, gnd for single supply operation) 8 c0 digital control pin 9 c1 digital control pin 10 inb+ amplifier b non-inverting input 11 inb- amplifier b inverting input 12 nc no internal connection 13 outb amplifier b output 14 v s + positive supply voltage (+6v for split supplies, +12v for single supply operation) 15 nc no internal connection 16 outa amplifier a output c0, c1 truth table c1 c0 function 00high bias setting 0 1 medium bias setting 1 0 low bias setting 11outputs disabled (power down)
ISL15100 4 fn8577.0 september 19, 2013 absolute maximum ratings (t a = +25c) thermal information v s + voltage to v s - or gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +13.3v ina+, inb+ voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd to v s + c 0 , c 1 voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v s + current into any input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ma continuous output current for long term reliability. . . . . . . . . . . . . . . . 50ma latch-up (tested per jesd78d, class ii) . . . . . . . . . . . . . . . . . . . . . . 100ma esd rating human body model (tested per jesd22-a114f). . . . . . . . . . . . . . . . . . 4kv charge device model (tested per jesd22-c101e). . . . . . . . . . . . . 1.5kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . 300v thermal resistance (typical) ja (c/w) jc (c/w) 16 ld qfn package (notes 4, 5) . . . . . . . . 53 16.5 maximum junction temperature (plastic package) . . . . . . . . . . . +150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . -40c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c junction temperature range . . . . . . . . . . . . . . . . . . . . . . - 40c to +150c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v s + = +12v, v s - = gnd = 0v, see figure 3, full bias (c 0 = c 1 = 0v), t a = +25c, unless otherwise specified. parameter description conditions min (note 6) typ max (note 6) unit dynamic performance -3db bandwidth bw figure 3, 2v p-p differential output at pins 180 mhz slew rate sr differential v out (v outa - v outb ) from -5v to +5v (10v p-p) 1200 v/s total harmonic distortion thd, low frequency, light load 200khz, differential 12v p-p , across 350 ? differential load -88 -67 dbc thd, low frequency, heavy load 200khz, differential 12v p-p , across 29 ? differential load -72 -68 dbc thd, high frequency, light load 4mhz, differential 12v p-p , across 350 ? differential load -64 -58 dbc thd, high frequency, heavy load 4mhz, differential 12v p-p , across 29 ? differential load -51 -48 dbc avg. multi-tone power ratio mtpr 2mh z to 50mhz, 25khz tone spacing, p line = 15.5dbm, cf = 15db -43 dbc off state multi-tone power ratio mtpr-of f 2mhz to 50mhz, 25khz tone spacing, p line = 15.5dbm, cf = 15db -55 dbc non-inverting input spot voltage noise eni f > 1mhz, spot noise voltage on ina+ and inb+ inputs separately 6nv/ hz non-inverting input spot current noise ini+ f > 1mhz, spot noise current on ina+ and inb+ inputs separately 13 pa/ hz inverting input spot current noise ini- f > 1mhz, spot noise current on ina- and inb- inputs separately 50 pa/ hz dc and input characteristics non-inverting input bias current i b+ non-inverting inputs, ina+ and inb+, at mid-supply voltage (note 7) -7 2 7 a non-inverting input bias current mismatch i b+dm difference between the ina+ and inb+ bias currents -0.5 0 0.5 a inverting input bias current i b- inverting inputs, ina- and inb-, at mid supply voltage (note 7) -90 -30 55 a
ISL15100 5 fn8577.0 september 19, 2013 inverting input bias current mismatch i b-dm difference between the ina- and inb- input bias currents -35 0 35 a inverting input bias current common mode i b-cm average inverting input bias currents (note 7) -90 -30 55 a input offset voltage v ioa, v iob voltage difference from ina+ to ina- and from inb+ to inb- -85 0 85 mv input offset voltage mismatch v iodm v ioa - v iob -5 0 5 mv input offset voltage common mode v iocm average offset voltage across the two inputs -80 20 80 mv differential mode output offset voltage v osdm output referred total effect of all differential dc error terms -7.8 0 7.8 mv common mode output offset voltage v oscm output referred total effect of all common mode dc errors -105 40 145 mv input headroom to positive supply (v s +) - v in(max) ina+ and inb+ required margin to v s + supply 3v input headroom to negative supply v in(min) - (v s -) ina+ and inb+ required margin to v s - supply 3v output characteristics output swing v o-open v s = 6v, differential r load 1k ? , each output pin voltage range 4.85 5.0 v v o-loaded v s = 6v, v o in linear region, differential r load = 29 ? , each output pin voltage range. 4.6 v v s = 6v, v o driven into the rail, differential r load = 29 ? , each output pin voltage range. 4.2 4.7 v output current i o linear output current (not short circuit) 300 400 ma power supply bipolar supply range v s symmetric supply, pin 4 at gnd for logic reference 4 6 6.6 v single supply range v s +single supply with v s - and pin 4 at gnd 8 12 13.2 v positive supply currents i s + (full bias) v o(diff) = 0v, c 0 = c 1 = 0v 27 32 37 ma i s + (medium bias) v o(diff) = 0v, c 0 = 3.3v, c 1 = 0v 19 23 26 ma i s + (low bias) v o(diff) = 0v, c 0 = 0v, c 1 = 3.3v 12 15 18 ma i s + (power down) c 0 = c 1 = 3.3v 5.5 7 8.5 ma c 0 , c 1 input high current i inh , c 0 or c 1 c 0 = c 1 = 3.3v (note 7) -150 -90 -30 a c 0 , c 1 input low current i inl , c 0 or c 1 c 0 = c 1 = 0v (note 7) -1.5 1 1.5 a c 0 , c 1 logic high voltage v inh pin 4 at gnd, logic reference pin 2 3.3 5.5 v c 0 , c 1 logic low voltage v inl pin 4 at gnd, logic reference pin -0.3 0 0.8 v notes: 6. compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design. 7. positive currents flow out of the pin. electrical specifications v s + = +12v, v s - = gnd = 0v, see figure 3, full bias (c 0 = c 1 = 0v), t a = +25c, unless otherwise specified. parameter description conditions min (note 6) typ max (note 6) unit
ISL15100 6 fn8577.0 september 19, 2013 applications information product description the ISL15100 is a differential operational amplifier designed for line driving in power line communications (plc). it is a low distortion, current mode feedback amplifier that draws moderately low supply current. due to the current feedback architecture, the ISL15100 closed-loop -3db bandwidth is dependent on the value of the feedback resistor. the desired bandwidth is selected by choo sing the feedback resistor, r f , and then the gain is set by picking the gain resistor, r g . feedback resistor values the ISL15100 has been designed and specified with r f =1k ? for a v = +16. as is the case with all current feedback amplifiers, wider bandwidth at the expense of slight peaking, can be obtained by reducing the value of the feedback resistor. inversely, larger values of the feedback resistor will cause rolloff to occur at a lower frequency. quiescent current vs temperature the ISL15100 was designed to have the quiescent current increase with temperature, which maintains good distortion performance at high temperatures. supply voltage range the ISL15100 operates with bipolar supply voltages from 4.0v to 6.6v (6.65v maximum). optimum bandwidth, slew rate, and video characteristics are obta ined at higher supply voltages. single supply operation if a single supply is desired, va lues from +8.0v to +13.2v (+13.3v maximum) can be used as long as the input common mode range is not exceeded. when using a single supply, be sure to either: 1. dc bias the inputs at an a ppropriate common mode voltage and ac-couple the signal. 2. ensure the driving signal is within the common mode range of the ISL15100. multi-tone power ratio (mtpr) g.hn plc uses ofdm modulation to digitally encode data for communication. a carrier spacing of 24.41khz is used in power lines, and 48.82khz is used in phone lines. in multi-tone signaling, linearity is shown in the mtpr measurement. mtpr measures the difference in power of a carrier tone vs. a missing tone. figure 4 shows ISL15100's mtpr performance for a narrow frequency span. disable linearity unlike dsl, communication in plc systems is half duplex meaning only one device can transmit at a time. when the line driver is not transmitting, it is disabled and the receiver is enabled. figure 5 shows the shar ed transmit and receive signal path of two ends. when txa is transmitting, optimal mtpr is achieved if txb is removed. since txb cannot be removed, the best mtpr occurs if the line dr iver is a very high impedance when disabled. r bm are resistors to limit fault currents, and to provide a driving impedance to the transformer, thus setting its frequency span. r bm is typically low in value (<10 ). -100 -90 -80 -70 -60 -50 -40 -30 1.50 1.52 1.54 1.56 1.58 1.60 tone power (dbm) frequency (mhz) mtpr figure 4. plc signal tones with 25khz spacing figure 5. tx and rx signal path. case1:[txa : on, rxa: off, txb: off, rxb: on]. case2:[txa: off, rxa: on, txb: on, rxb: off]
ISL15100 7 fn8577.0 september 19, 2013 pc board design recommendation to minimize parasitic capacitance in the ISL15100 design, consider laying out short output traces. also, select low capacitance protection devices, and use line transformers with low interwinding capacitance in the signal path. the supply decoupling capacitors must be close to the supply pins to minimize parasitic inductance in the supply paths. high frequency load currents are pulled through these capacitors, so placement of the 0.1f capacitors close to the supply pin(s) improves dynamic performance. the higher value 4.7f capacitors provide low frequency decoupling, so they can be placed farther from the supply pins. the ISL15100?s thermal pad (ep) should be connected to v s - (ground in single supply applications). for good thermal control, include a thermal pad in the layout footprint, as shown in the ?typical recommended land pattern? on the ?package outline drawing? page. adding vias to this thermal pad helps dissipate heat away from the package. the ISL15100 evaluation board uses four 10mil (hole size) vias with 20mil diameter pads. thermal resistance and power dissipation thermal resistance for ju nction to ambient, t ja , is +53c/w. the power dissipation at 12v supply is 600mw. the ambient temperature allowed given the maximum junction temperature of +150c is: t a t j ja pd ? = (eq. 1) t a +150 c53 cw ? () ? ? 600mw +118 c == ina outa outb 1 4 sw1:1 2 3 sw1:2 vs+ c2 0.1uf c4 0.1uf rsb 49.9 r11 10k rfb 1k rfa 1k rsa 49.9 c1 4.7uf c3 4.7uf rext3 22 2w rext4 56.2 rext1 243 rext2 243 + + nc 1 2 3 gnd 4 nc 5 nc 6 vs- 7 c0 8 c1 9 10 11 nc 12 13 vs+ 14 nc 15 16 _ _ + + u1 ISL15100irz s/n=cmhz5229b inb r1 0 r2 0 l2 l1 tp2 d4 open d3 open d1 open d2 open rga open rgb open rlb 3.9 1/4 w rla 3.9 1/4 w r4 0 rcg 133 r3 0 d5 4.3v zener diode 2.9v@ 300 ua j1 vs+ j2 gnd j3 vs- vs+ vs- vs- vs+ vs+ vs+ vs- tp5 gnd tp4 gnd tp1 tp9 ina tp10 inb tp12 vs+ tp13 vs- tp14 gnd r9 100 r10 100 figure 6. ISL15100 evaluation board
ISL15100 8 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8577.0 september 19, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change september 19 2013 fn8577.0 initial release.
ISL15100 9 fn8577.0 september 19, 2013 package outline drawing l16.4x4h 16 lead quad flat no-lead plastic package rev 0, 1/12 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view see detail "x" 0.30 0.05 base plane pin #1 5 8 ( 3 . 6 typ ) (12x0.65) (16x0.30) 0 . 20 ref +0.03/-0.02 c 5 4 0.10 c m index area (4x) 0.15 pin 1 6 4.00 12 4.00 9 a b 4 0.65 12x 13 4x 1.95 16 1 6 c seating plane 0.10 c ab 16x 0.5500.05 2.40 ( 2.40) 0.900.10 (16x0.75) 2.40 index area
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